*** M E M O R U M ***

But that is cheating :shock: It still frustrates me that I have to use proprietary tools to design and program the CPLDs. In the old days I wrote my own assembler and built my own EPROM eraser and programmer. Perhaps I should have done a discrete logic design. In order to get the board made commerci...

My first attempt at constructing the CPU PCB failed. I attempted to use a piece of PCB which I have had for too many years. The photo-resist has obviously got old, and relatively insensitive to UV. Failed_PCB.jpg During development the etch-resist has failed to come completely away from the copper. ...

Looking at the data sheets, it seems to me that there are two significant differences between the BAV199 and a pair of 1N4148: The BAV199 diodes have a reverse leakage current of only 5nA, as opposed to 25nA for the 1N4148. The two diodes in a BAV199 will be very closely matched, and thermally coupl...

Added the ROM address jumpers as suggested by Martin. A bit of a squeeze to fit them onto the PCB without moving everything. Not sure that I will need them. My present thought is that the ROM will just contain a boot loader, and everything else will be loaded from SD card. It makes development easie...

Good point Martin, I will see what I can fit in.

As suggested earlier, I have revised the circuit diagram to have a separate ROM Write Enable signal. The revised VHDL for this is: library ieee; use ieee.std_logic_1164.all; entity Z180_EC_Mem_CPLD is port ( data : inout std_logic_vector(3 downto 0); addr_lo : in std_logic_vector(7 downto 0); addr_h...

Just looking back at the MTX circuit diagram in the manual. It uses the six inverters in a 74S04 chip as the clock source. Three of the inverters are used as output drivers, one for the CPU, one for the CTC and one for everything else, The CPU and CTC drivers each have 330R pull-ups to 5V, presumabl...

Attached is the proposed circuit diagram for a cut down board, just CPU and memory. The UART built into the Z180 means that this board will be testable as-is. This design includes an edge connector with the minimum signals required for I/O expansion, assuming just 8-bit I/O addresses. Using an EPM71...

Martin, That is more or less what I am proposing in terms of splitting into multiple boards. I will probably use my usual technique of ribbon cable and IDC connectors for a backplane. However the individual (daughter) boards will be hand etched PCBs and will need holes drilled for each of the IC soc...

I have a draft PCB layout, see attached. Only slight problem, it is 9 inch x 5 inch. Too big to be convenient, and I am not sure whether my UV light box is big enough to develop a board of that size. Two options: Use a different construction method. The obvious alternative method is to use "perf boa...