*** M E M O R U M ***

Paul, Glad you got it compiled at least. I don't know why it should be giving the error message, but then I have only ever compiled and run the program on Linux. Sorry about the lack of documentation. As mentioned it was originally written for my own use. It might be better to start by playing with ...

Paul,

Something I wrote, and omitted from the ZIP file. Apologies for that

I have included it in the attached ZIP which also has some further enhancements to decoding the WAV file, derived from plagiarising your mtx2bas code.

Claus,

It should compile with MinGW or MinGW64. You will also need the wxWidgets library.

With regards to comments, the code was originally written just for my own use to solve Paul's challenge.

See also this post.

Attempting to scan a tape audio file for Claus at MemoFest yesterday uncovered a couple of limitations in my TapeView program: The BASIC listing was missing a space before some keywords when they appear in the middle of a statement. This has now been fixed. The listing was failing to recognise NODDY...

Another very enjoyable Memofest. Thanks to Andy and family for hosting :D Claus showed a couple of new game conversions, one of which was used for the high score competition, Having had practice Claus thrashed the rest of us :lol: Andy demonstrated one of his latest developments, a ROM add-on card w...

Following on from Martin's comment about re-factoring the VHDL, I have attempted to draw out the SD Card interface as a circuit diagram.

Martin, I think all the latches are fundamental to the design, although if anyone can come up with something better I would be interested. Dave, I have EPM7032 and EPM7128 chips from Lez. Also a USBBlaster clone (although I haven't tried that yet). Anything else I would have to buy. I could, but bet...

It appears that my proposed SD Card interface is pushing the limits of the small CPLD I am planning to use. My initial VHDL was: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Z180_EC_Util_CPLD is port ( data : inout std_logic_vector(7 downto 0); addr : in std_log...

I need to get some more materials before I can have another go at etching a board. However, assuming that I eventually succeed with that, attached is a preliminary design for the second board to contain: SD Card interface Real Time Clock Floating Point Unit This board layout is looking a bit empty. ...