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Re: Bootstrap and boot blocks

Posted: 27 Jun 2019 23:39
by EtchedPixels
Umm try 2. This one I tested exactly as is on my MTX.

uncompress this one and see if it's any better. Same path, new one has an SHA hash of 07fedf508dab16be0f1f1ef058b5ea9a61659e42 and is 1488125 bytes long (just in case some crapware ISP proxy is caching the old one...)

The layout is PC partition tables. As that includes space at the start of logical block 0 the boot sector lives there and the OS loads from the PC partiton boot area (sectors 1-2047), and then runs. No BDOS or BDOS layout involved. Other than using the BIOS at boot it takes over completely.

You need 3 48K banks plus common.


Re: Bootstrap and boot blocks

Posted: 27 Jun 2019 23:55
by Dave
It will be tomorrow before I can try it. Maybe I screwed up writing the image or maybe it’s my CF card, I will try a card that
I know to work with CFX tomorrow.

I’m sorry, but I still don’t see how you can get 3 x 48k banks out of a 64k computer? CFX-II has an extra 512k that’s usually used for the SiDisc, are you using that? CFX-I has no additional RAM so is limited to the 64k of the MTX512, so maybe won’t work?


Re: Bootstrap and boot blocks

Posted: 28 Jun 2019 00:02
by EtchedPixels
You need a memory expansion as well. So you need at least 160K of RAM.

I'm running it with a CFX-II and one of Andy's memory cards. It would be possible to make it run (but more slowly) in 112K but 64K is right out. SiDisc is I/O mapped so you could use it for faster swap (versus CFX-I at least) but not as working memory.


Re: Bootstrap and boot blocks

Posted: 28 Jun 2019 00:28
by Dave
Ah, OK, very few people will have CFX and an extra RAM card, up until now, there hasn’t been any software that would use the extra RAM.

I do have a RAM card though and will plug it in tomorrow


Re: Bootstrap and boot blocks

Posted: 28 Jun 2019 10:12
by Martin A
No ram expansions for either of the MTXs here. However that image seem to be working OK on the MTX plus which is configured for 448k.

There's a few odd characters, and an "X" appearing on the end of lines.
MTXplus with Fuzix
MTXplus with Fuzix
fuzix.jpg (527.75 KiB) Viewed 2110 times
I'm wondering if the odd characters are down to scrolling getting out of alignment ??

NB don't worry about the colours that was just a SCART plug not fully pressed home!

Re: Bootstrap and boot blocks

Posted: 28 Jun 2019 11:36
by EtchedPixels
That looks to me like a VDP timing problem as a first guess and maybe a side effect of you using a TMS9958 and my interrupt handling.

What happens to the CPU speed when accessing the VDP, what clock is it running at and are the VDP clock and CPU clock derived from each other or separate ? Do you have \WAIT wired to the 9958 (so I can use r25 bit 2) ?

What is the correct number of clocks between VDP accesses on the MTXPlus ?

Does your output side support the higher resolutions the 9958 can do ?


Re: Bootstrap and boot blocks

Posted: 28 Jun 2019 11:52
by Dave
Hi Alan,

I will try and get it tested on my MTX today, but just wanted to say that it would be great on MTXPlus+ if you can add support for it. It does support 80 columns and has more RAM and a much faster clock speed


Re: Bootstrap and boot blocks

Posted: 28 Jun 2019 12:19
by Martin A
The MTXplus has some very fancy clock controls designed by Tony Brewer. The CPU is booting at 4mhz, but can be switched up to 16mhz in 16 steps. ... clocks.htm

The same system keeps track of VDP writes and automatically inserts Z80 wait states when the CPU is running faster than 4mhz. /wait from the VDP is wired through that system so will be active if the CPU is switched up, it's enabled by the MTXplus rom early in the boot sequence.

The Fuzix system will be running at 4mhz since it won't know how to program the variable clock, which means the wait system is inactive.

The clock control utility from MTX basic and the one for CPM both re-program the CTC to keep the interrupts at 125hz. The CTC uses 2 daisy chained counters instead of the usual one in order to keep the system tick at 125hz.

In 40 column text mode the V9958 isn't as responsive as the 9929 ... ing-2.html so that could be the issue with scrolling, since the wait state system won't be active.

To set an 8mhz clock, sent &70 to port &FF, and program the CTC with time constants 100 and 40 and everything would be fine.

The full source for the SDX command USER SPEED is bellow. The data table sits at 3F00 in the SDX rom simply because it made the pointer maths easier. USER SPEED with no value prints the current clock speed. If there is a value or variable after the command the CPU and CTC will be set up with that speed rating (value mod 16 really,it doesn't range check. USER SPEED 1 is the same as USER SPEED 17)

Code: Select all

;report back the current CPU settings
inc DE               ;step past the last character of the command
;;check to see if there is a number following the command
ld a,(DE)
cp &FF
JR z report_CPU_speed     ;check the end of line marker
call getnxt          ;hopefully this will read the value/variable
ld a,c               ;get the low byte
add a,a
add a,a
add a,a
add a,a              ;shift to the top 4 bits
out (&FF),A          ;and set the clock
add a,5              ;offset into the table of the CPU frequency data
LD H,&3f
LD L,A               ;HL now holds pointer to CPU clock data.
ld a,(hl)
ld (CPU_freq),A
inc HL
ld a,(hl)
ld (CPU_freq+1),A
inc HL
;now need to set up the CTC counters
Call IJinit             ;turn off interrupts and reset the CTC just in case
LD   A,&05              ;disable interrupt, prescale 16
OUT  (&08),A
ld a,(hl)               ;get time constant 1
OUT  (&08),A 
inc HL
LD A,&D5                ;Enable interrupt, counter mode, 0, rising edge, 
                        ;0, time constant follows, no reset, control word
OUT (&0B),A
ld a,(HL)
OUT (&0B),A
                        ;fall through to report the speed
RST &10
DB &8F
DB 13,10
DS "Master clock:"
ld H,&3f
in a,(&FF)
and &F0
ld l,a                  ;HL now points to the 5 byte string for the current speed description 
ld b,5
ld a,(hl)
;rst &28
;db &AC
out (1),a
inc HL
DJNZ report_cpu_loop
; call newline
RST &10                ;print a "newline" a different way
DB &82
DB &0D,&0A

;extended CPU speed table
org 3f00
;revised clock system has 16 available frequencies driven from a 32mhz master clock
;table format 5 byte string, 2 bytes major/minor speed, CTC clock settings, 7 bytes padding to make
;entries 16 bytes for quick access
; stored at the end of the rom to make setting up the ponter easy
DS " 4.00"
DB 4,0
DB 50,40
DB 0,0,0,0,0,0,0

DS " 4.57"
DB 4,57
DB 127,18
DB 0,0,0,0,0,0,0

DS " 4.92"
DB 4,92
DB 107,23
DB 0,0,0,0,0,0,0

DS " 5.33"
DB 5,33
DB 127,21
DB 0,0,0,0,0,0,0

DS " 5.82"
DB 5,82
DB 97,30
DB 0,0,0,0,0,0,0

DS " 6.40"
DB 6,40
DB 100,32
DB 0,0,0,0,0,0,0

DS " 7.11"
DB 7,11
DB 127,28
DB 0,0,0,0,0,0,0

DS " 8.00"
DB 8,00
DB 100,40
DB 0,0,0,0,0,0,0

DS " 8.53"
DB 8,53
DB 251,17
DB 0,0,0,0,0,0,0

DS " 9.14"
DB 9,14
DB 127,36
DB 0,0,0,0,0,0,0

DS " 9.85"
DB 9,85
DB 107,46
DB 0,0,0,0,0,0,0

DS "10.67"
DB 10,67
DB 127,42
DB 0,0,0,0,0,0,0

DS "11.64"
DB 11,64
DB 253,23
DB 0,0,0,0,0,0,0

DS "12.80"
DB 12,80
DB 200,32
DB 0,0,0,0,0,0,0

DS "14.22"
DB 14,22
DB 127,56
DB 0,0,0,0,0,0,0

DS "16.00"
DB 16,00
DB 200,40
DB 0,0,0,0,0,0,0

Re: Bootstrap and boot blocks

Posted: 28 Jun 2019 12:26
by Dave
Hi Alan,

some good progress (with the new image). I have my (Andy's) Memory card installed, but obviously don't have it pinned correctly, so there is not enough memory available. I need to try and find where I put the pinning details for the card, but I have to go out for a while - will get to it later.

(BTW - this is using CFX-I in 40 column mode)
IMG_8631.jpg (618.57 KiB) Viewed 2106 times

Re: Bootstrap and boot blocks

Posted: 28 Jun 2019 12:36
by Dave
PS, just randomly changed one jumper :-)
So the setup is probably not right, but did get to the boot stage
Booted off hda1 and it started to mount the root fs, saw the init version number and the CF card flashed as data was loaded before it hung

Will try to check the memory setup, but now I AM going out :-)