Another Home-Brew - Z180

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Bill B
Posts: 165
Joined: 26 Jan 2014 16:31

Another Home-Brew - Z180

Post by Bill B » 13 Aug 2019 16:06

Having taken advantage of Lez Anderson's extremely generous offer of free chips for a second time, I thought I should nail my colours to the mast and publicly commit to doing something with them.

What attracted me to the latest offer from Lez was the inclusion of Z180 CPUs. The idea of building a fast system with a large amount of RAM (for a Z80) appealed.

What I am currently planning is:
  • Z180 CPU clocked at 20MHz.
  • 1 MByte RAM.
  • Boot ROM. Not sure whether I will have the option to switch this out once booted.
  • SD card for storage.
  • Just because I have them amongst the first lot of chips from Lez:
    • DS12887 Real Time Clock.
    • AMD 9511 Floating Point Unit.
I am planning SD card rather than CF for two reasons:
  • The greater availability of SD cards.
  • Just to avoid repeating what Martin has done.
I was originally thinking of attempting to implement the 4-bit parallel SD card interface, but the ready availability of SD card break-outs with built in 5v to 3.3v level shifters, such as these decided me on using SPI. To achieve best speed I intend to implement a hardware assisted SPI interface, using ideas from here, but implemented in CPLD. Which means that I will have to learn how to program CPLDs :!:

I also need to take a look at what Andy did for Rememoriser.

For the first stage I intend to use one of the Z180 UARTs for user interface. For a later stage I will probably add a version of my Propeller VGA display driver. Alternately, I have a couple of 1980's 640x200 monochrome LCD displays which I know a Propeller can drive.

In terms of maximising performance of the main CPU there are advantages to continue to use a UART for keyboard input, and if what is received is keyboard press and release events rather than character codes it can be just as versatile as directly interfacing the keyboard. So another possible extension is a microcontroller keyboard interface. Various options for the actual keyboard:
  • I have an existing matrix keyboard left over from an old project.
  • PS/2 keyboards are not so common today, but are easy to interface.
  • USB keyboards require a more powerful microcontroller.
  • Keyboards are cheap. Take one apart and there is probably a matrix keyboard inside.
I am not planning to produce a games machine. I am more interested in OS experimentation. Ideas of interest:
  • The SD card interface.
  • CPM/FAT. The idea is to produce a BDOS which has largely the same ABI as CP/M, but which produces a FAT file system on disk. The function calls will be the same, and the FCB will differ only in the contents of the allocation section (bytes 16-31). Low level utilities will have to be re-written, but I would expect most user programs to run unmodified.
  • CP/M Plus. Hence the real-time clock.
  • Fuzix.
I will report my, probably slow, progress here.

Martin A
Posts: 410
Joined: 09 Nov 2013 21:03

Re: Another Home-Brew - Z180

Post by Martin A » 14 Aug 2019 19:14

I'll be very interested to see the SPI results. CF is getting harder to source at reasonable prices do SPI/SD has more of a future.

Even cheaper than SD, if you can mount it is something like: ... 8q4g%3D%3D 8meg x 8 storage for under a pound!

The CPM meets FAT thing was done for MSXDOS, the early version was FAT12, but I think the later one might have been FAT16. Were you thinking of using FAT32 ?

Bill B
Posts: 165
Joined: 26 Jan 2014 16:31

Re: Another Home-Brew - Z180

Post by Bill B » 18 Aug 2019 21:56

Attached is a planned circuit diagram.

The Z180 has a 1MB external address space which is mapped onto the 64KB address space of the Z80 core in three areas, which the Zilog documentation designates as (from low internal address to high):
  • Common Area 0
  • Bank Area
  • Common Area 1
The boundaries between these areas can be set at 4KB intervals, as can the starting physical address of the latter two areas. So Common Area 1 is also potentially banked.

However Common Area 0 always starts at logical and physical address zero. To make this area more useful, I propose to add three modes of mapping the Flash ROM onto the physical address space:
  • 128KB linear ROM addresses followed by 896KB of RAM. This will be the boot configuration.
  • 16KB of banked switched ROM followed by 1008KB of RAM.
  • Full 1MB RAM with no ROM.
The CPLD will contain a register written by a Z80 OUT command to select the mapping mode and ROM bank. The three high addresses of the ROM go via the CPLD which can either copy the Z180 addresses or supply the bank address depending upon the mode selected. ROM and RAM chip select lines also depend upon the selected mode. This register will also have a bit to enable writing to the Flash ROM for updates.

The Z180s that Lez supplied are rated at 33MHz. However I intent to run it at 20MHz. As per my earlier post, I am planning to use the UART for user interface (at least to start) and 20MHz / 2048 is within 2% of 9600 baud.

The datasheet for the Z180 I have in my copy of "Z80 Family Data Book (January 1989)" indicates that the crystal or oscillator input needs to be twice the CPU frequency, so I purchased a 40MHz oscillator module. I subsequently found from later datasheets that modern Z180s can run at equal or twice the input oscillator frequency. I therefore run the oscillator module output through the CPLD so that I could potentially divide the frequency into the Z180.

I etch my own PCBs, which imposes some limitations. There is a limit to the minimum track width I can preserve, which means at most one track between a pair of IC pins. Also there are no through plated holes, which means that each connection to a pin must be on the lower surface of the PCB. With DIP chips I can connect a data bus to the pins on one side of the chip and then weave it between the pins on the other side and on to further chips. However with PLCC sockets I can weave past the outer pins to get to the inner ones but then cannot get from the inside back out because of the connections opposite. As a result, the two PLCC chips (Z180 and CPLD) will come at the two ends of the address and data buses, with the other chips between.

To provide some scope for expansion I propose to use the spare pins on the CPLD to provide a buffered data bus and a few address and IO control lines.

Next step is to attempt to lay out the PCB.
Draft Circuit Diagram of Z180 Experiment
(166.91 KiB) Downloaded 3 times

Martin A
Posts: 410
Joined: 09 Nov 2013 21:03

Re: Another Home-Brew - Z180

Post by Martin A » 19 Aug 2019 23:17

Which Z180 is it, the likes of Mouser seem to imply the 20mhz part is 3.3v, while the 10mhz and 33mhz are 5v. The data sheet isn't very clear either.

Bill B
Posts: 165
Joined: 26 Jan 2014 16:31

Re: Another Home-Brew - Z180

Post by Bill B » 20 Aug 2019 08:10

What I have is Z8S18033VSC.

The way I read the datasheet I have:
  • Z8S180 is for 5v parts
  • Z8L180 is for 3.3v parts.
It also suggests that Z8L parts are only available up to 20MHz (the higher speed needs a higher voltage).

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