CFX-3, a work in progress . . . .

Modern, Memotech inspired, hardware projects
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CFX-3, a work in progress . . . .

Post by Dave » 22 Jun 2018 06:11

What have we (well, Martin really), been doing lately?

Working on the 80 column emulation for MTX computers.

The background . . . .

Bill's Parallax Propeller 80 column card replacement for the MTX is a really great piece of work. It has allowed us to include 80 column card functionality with our CFX disk drive replacement board (as CFX-II, ... /cfxii.htm) at very little additional cost. As well as having a useable 80 column board interface, the Propeller also allows the MTX VDP output to be shadowed to drive the VGA monitor with much better quality output than from the MTX RF or composite video outputs.

Unfortunately though, some VGA monitors exhibit a noticeable amount of "noise" when displaying the 80 column card output. The "jitter" is possibly due to the Propeller using a PLL to generate its faster clock speeds, rather than allowing a higher frequency oscillator to be used. Although the 80 column display is perfectly useable, it is not perfect on some monitors.

The result . . . .

Martin wondered whether it might be possible to use a CPLD to generate VGA output from an emulated 80 column board. I found a project on the web that did just that and Martin used that as the basis for a new "80 column card" to be integrated into CFX. Leading to . . . .

CFX3 !

I am working on a CFX3 section on the website, but in the meantime, over to Martin to describe how the CFX3 VGA solution has come to pass . . . . .


Martin A
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Re: CFX-3, a work in progress . . . .

Post by Martin A » 22 Jun 2018 13:18

The basic idea that started CFX-3 was to create a video signal using a high speed oscillator do drive the pixel clock, instead of a PLL. That would hopefully eliminate the jitter on the display that we were seeing from the propeller in the CFX-II once the board had warmed up.

I initially thought we should try and create a cut down 6845 type device within the CPLD.

After searching the net, Dave found this thread over on the forum that has some really useful ideas that vastly simplifies the job of producing the video output.
HTTP:// ... A&start=15

The big trick to simplifying the logic was to use 2, dual port rams, in a 16 bit wide configuration at the CPLD side, while accessing them as 8bit memories on the CPU side. Dual port ram relieves the contention issue of how to deal with the CPU and VGA controller accessing memory at vastly different speeds.

While the CPLD side addresses the 2 rams at the same time. The CPU side address connections to the rams are offset by 1 to allow the 2 memories to be interleaved so that the CPU side sees alternating character and colour data.

The MTX display needs 2k of ram for each of the character and colour memories, as the display is 80 x 24. That would require 20 scan line per character to make up the 480 lines on the basic VGA display. That in turn requires 32 bytes for each character definition, with the last 12 byte being unused.

The MTX 80 column output is RGB and not RGBI so uses 3 bits each for foreground and background colour, the other 2 bits of attribute data are reserved for the flash and Block graphic attributes.

The original board used 2 character roms one for the character set, and the other for block graphics. 256 characters x 32 rows requires 8k of ram, the smallest easily available flash chips are 128k so it made sense to use one ROM for both ASCII and the block character sets.

The ROM actually has 4 full character sets programmed in. The one is the standard one from the 80 column board, doubled up to fill the 20 line resolution of the new display. That's followed by the inverted version of the same characters. The 3rd set is the block graphics, those are based on a 4 dot wide, 5 line high, "pixel" making all the pixels the same size. The 4th set is the inverse block graphics.

The display rom ends up being 32k long, with A0 to A4 being the row definitions, A5 to A12 is the character number, A13 is invert and A14 for block characters. The other 2 address bits are just tied low, but in theory could be jumpered to allow additional characters.

What that basically means is the 16 bit wide memory as seen by the CPLD is split 6 bits for colour and 10 for the character data, and each follows a different path over the board.

Of the 10 bits of character data 9 go direct to the character rom, the flash attribute but however goes to a high speed NAND gate where it's combined with a counter output from the CPLD before being connected to A13 on the ROM which is effectively the "flash" bit.

If both the counter and flash are high, the inverted character is selected. If either is low either because the character isn't flashing, or because the counter is low the normal character is used.

The 8 bits output to the character rom are loaded into a shift register, which clocks out the pixel data in a serial stream.

The colour data has a much shorter path, the 6 bits of colour data are latched on time with the shift register, and feed a multiplexer. Only 3 of the 4 channels are used. The pixel stream from the shift register then determines the binary data presented to the drive resistors on the VGA output.

The CPLD calculates the timing for the shift register and colour latch, the horizontal and vertical syncs, the row counter for the character rom and the flash counter. It's also controlling the memory paging for the video memory and the control rom, as well as the I/O ports for the Silicon Disc and the 8 bit compact flash based IDE interface.

Martin A
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Re: CFX-3, a work in progress . . . .

Post by Martin A » 22 Jun 2018 13:34

busy board.jpg
The board is almost full
busy board.jpg (115.78 KiB) Viewed 885 times
It's quite a busy board, on left is the VGA connector and the 3 drive resistors.

Above than is a 512k nvram chip holding the silicon disc, with SiDisc counter and latches surrounding it.

Next on the left is the shift register and output multiplexer.

Centre top is the CPLD and Compact flash. Below the CPLD is the character rom and 25.175 MHz clock partly obscured by the CPLD programming cable.

Also under the cable is the high speed NAND gate controlling the flashing. The 16 pin counter chip under the rom is now redundant as of the last CPLD update and will be removed.

Under the CF adaptor is the colour latch.

The 2 x 48 pin chips are the dual port ram for attribute and character data. Above that is another rom that holds the CPM boot code and the SDX basic extensions.

The empty socket in between is from another logic chip who's function is now contained in the CPLD.

And this is how the output looks.
The output from CPM
output.jpg (71.07 KiB) Viewed 885 times

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Re: CFX-3, a work in progress . . . .

Post by thewiz » 22 Jun 2018 14:36

Looks nice and clear from the photo. Well done.
THIS is what Memotech is doing now.

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Re: CFX-3, a work in progress . . . .

Post by Martin A » 23 Jun 2018 19:11

And some more pictures:
VDP boot screen
boot40.jpg (107.13 KiB) Viewed 831 times
The VDP display on boot. It will be pretty familiar to anyone that's played with a CFX or CFX-II. On a colour screen it's the familar blue and white.

The CX boot option is intended to help recover if the SiDisc gets corrupted and prevents the system booting. CPM will boot off the SiDisc if it sees the start of a system track. The SiDisc is also visible from SDX basic as the "F:" drive (along with B, C, and D. E if configured is only visible to CPM). The basic extensions can't format the F drive that has to be done from CPM.
The 80 column output
boot80.jpg (52.34 KiB) Viewed 831 times
Because it only has one output mode, the 80 column hardware doesn't need any initialising, unlike the 6845 of the original Memotech board. Which means on boot it will display totally random display of whatever happens to emerge from the video ram on power up. On a CPM boot that's no problem as the firsts thing the CPM boot rom does is clear the screen. For a boot to basic rather than just add code to clear the display, I added a spalsh screen.

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Re: CFX-3, a work in progress . . . .

Post by 1024MAK » 05 Jul 2018 20:42

Nice work Martin and Dave 8-) :D


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