System test rom/Board

Modern, Memotech inspired, hardware projects
Martin A
Posts: 406
Joined: 09 Nov 2013 21:03

System test rom/Board

Post by Martin A » 18 Apr 2019 18:07

Elsewhere viewtopic.php?f=9&t=419 I've mentioned building a board to test a black screening MTX. Rather than drag that thread off topic I've started a new one.

The board itself is basically just 2 chips and some configuration jumpers. There's a 32k or larger (e)eprom or flash and a 16V8 GAL. I'm using a 128k Amic flash as it's easier re-programming. However changing the bottom (green) jumper to the right hand setting would allow a 28 pin 27C256 eprom to be used instead.

The board's been angled to march the keyboard slope, the end plate won't fit with the board in place, but that's not really an issue. If an MTX is broken enough to need the board, the case will be open anyway.

The top 3 jumpers are to the right in the photo indicating that all 3 system roms are to be supported on the board. The red jumper selects either the standard 8k rom, or an image with some basic diagnostics.
close up.jpg
Close up of the test board in place
close up.jpg (71.5 KiB) Viewed 460 times
You'll notice the empty socket, that's one of the 74xx157 ram multiplexers. With that pulled booting the system on the standard roms will produce the classic black screen and tone.

Booting from the alternate boot rom, even with the ram disabled, currently brings up this screen.

The ram test need some more work, possibly with an option to check the rom paging as well as the ram. But the screen and keyboard handling system is working.
Test rom running.jpg
The test rom needs no ram
Test rom running.jpg (114.29 KiB) Viewed 460 times
To show there's no cheating you can see the motherboard in the photo with empty multiplexer and rom socket.

The last photo has the 74xx157 in the socket and show the MTX at ready, despite there being 3 empty sockets where the OS should be.
Booting basic with no onboard ROM.jpg
No OS !
Booting basic with no onboard ROM.jpg (120.94 KiB) Viewed 460 times
Programming a Z80 to run with ROM only isn't as complicated as it might seem. There are enough registers available to make a lot of tasks doable.

With no ram you can't:
  • call subroutines
    push/pull temporary data
    use interrupts
The test rom uses the IX and IY registers as a crude 2 level stack in the absence of a memory stack. The CALL instruction is replaced by one of 2 macros that assembles as

Code: Select all

LD IX,return            ;or IY
JP subroutine
return:
Because the jump opcodes have the same conditional options as call it's possible to code the equivalent of a conditional call, though the code currently in the test rom doesn't need to use that. Subroutine returns is replaced by

Code: Select all

JP (IX)            ;or JP (IY)
There's a restriction that it's only possible to go 2 levels deep, and the right "return" opcode has to be used. That needs a little thought in preparing the code to make sure subroutines called from subroutines use the "right" call/return macros.

Conditional return isn't possible though that can be dealt with by having a conditional jump to the unconditional "return" instead.

The Z80's alternate register set are awkward to use as general registers as all 3 register pairs swap at the same time. Making it hard to change just 1 register or register pair. I've used more macro's instead to give 6 bytes of "ram" accessible to the A register. They generate the following code. The assembler will take a number 0-5 and convert that to BCDEH or L. So that the "ram" address can be defined as equates.

Code: Select all

; store macro
EXX
LD %1,A
EXX

;get macro
EXX
LD A,%1
EXX
Swapping the A register with it's alternate has no real penalty and can com in handy.

Basically the test rom is written as if it was an 8080 with a 2 level stack and 6 bytes of ram. Restricted yes. but not too restricted.


*edited to correct typo
Last edited by Martin A on 20 Apr 2019 17:47, edited 1 time in total.

stephen_usher
Posts: 188
Joined: 27 Nov 2016 19:58

Re: System test rom/Board

Post by stephen_usher » 18 Apr 2019 18:16

I'm pretty sure that this is going to be a vital maintenance tool in future.

Martin A
Posts: 406
Joined: 09 Nov 2013 21:03

Re: System test rom/Board

Post by Martin A » 18 Apr 2019 19:58

I "draw" my board layout's in Excel. For matrix boards, the layout is as seen from the back, I then just have to connect all of the points with the same name. Pretty much all the wiring on the rom board is either edge connector to chip or chip to chip. The power connections do visit multiple points.

Not shown on the wiring map, but present on the test board are a couple of 0.1uf 0805 SMD capacitors on the back for power supply smoothing. It's such a small board I've not included a bulk decoupling capacitor.
Layout.pdf
Board layout
(225.2 KiB) Downloaded 20 times
The GAL code is pretty straightforward, it's written for clarity leaving the complier to simplify out all the redundancies. None of the resulting equations uses more than 3 of the 8 available terms on a 16V8.

The GAL generates the chip select and 4 upper address lines. Read, data and the remaining address lines come straight from the edge connector.

Code: Select all

Name     DiagRomBoard4 ;
PartNo   00 ;
Date     12/04/2019 ;
Revision 01 ;
Designer Engineer ;
Company  None ;
Assembly None ;
Location  ;
Device   G16V8 ;

/* *************** INPUT PINS *********************/
PIN    1  = A13                     ; /* Z80 upper address bits          */ 
PIN    2  = A14                     ; /*                                 */ 
PIN    3  = A15                     ; /*                                 */ 
PIN    4  = R0                      ; /* ROM page port bits              */ 
PIN    5  = R1                      ; /*                                 */ 
PIN    6  = R2                      ; /*                                 */ 
PIN    7  = RELCPMH                 ; /* ROM enable low - CPM high       */ 
PIN    8  = MREQ                    ; /* CPU Memory request              */ 
PIN    9  = J1                      ; /* Configuration jumpers           */ 
PIN   11  = J2                      ; /*                                 */ 
PIN   12  = J3                      ; /*                                 */ 
PIN   13  = J4                      ; /*                                 */ 

/* *************** OUTPUT PINS *********************/
PIN   14  = X2                      ; /* ROM upper address bits          */ 
PIN   15  = X1                      ; /*                                 */ 
PIN   16  = X0                      ; /*                                 */ 
PIN   17  = CS                      ; /* ROM chip select                 */ 
PIN   18  = X3                      ; /* extra addrss line for 128k device */
FIELD address = [A15..A0] ;
FIELD pageRom = [R2..R0] ;

/* ROM is selected in ROM mode only */
/* RELCPMH and MREQ checked in the chip select so not needed in the indivisdual rom equations */ 

!CS =
  !RELCPMH & !MREQ & !ROMA
# !RELCPMH & !MREQ & !ROMB
# !RELCPMH & !MREQ & !ROMC
# !RELCPMH & !MREQ & !ROMX
;

/* interim equations for each rom select */
/* Fixed rom is 0 - 8k area, paged rom 8k -16k */
/* 128k rom has room for 16 images */

/* J4 is low J1-J3 switch in individual replacement rom images  */
!ROMA =  J1 &             !J4 & address:[0000..1FFF]             ;    /* Fixed rom area replacement OS rom        */
!ROMB =        J2             & address:[2000..3FFF] & pageRom:0 ;    /* Paged rom area replacement system rom B  */
!ROMC =              J3       & address:[2000..3FFF] & pageRom:1 ;    /* Paged rom area replacement system rom C  */

/* J4 is high J1 switches in replacemnt A image                 */
!ROMX =  J1             &  J4 & address:[0000..1FFF]             ;    /* Fixed rom area replacement OS rom        */

/* X0 address bit is low for rom images 0 ad 2*/

!X0= 
  !ROMA
# !ROMC
;

/* X1 address bit is low for rom images 0 & 1 */
!X1 =
  !ROMA
# !ROMB
;
/* X2 address bit is low for 32k images       */

!X2 = 
  !ROMA
# !ROMB
# !ROMC
# !ROMX
;
/* X3 address bit is low for 32k images       */

!X3 = 
  !ROMA
# !ROMB
# !ROMC
# !ROMX
;


I'll publish the rom code later, once the ram test is a bit more robust. The current simple check is so simple it can't detect a missing/defunct '157 multiplexer !

Pernod
Posts: 15
Joined: 21 May 2017 17:26
Location: Croydon, UK

Re: System test rom/Board

Post by Pernod » 18 Apr 2019 20:05

Would really like to run your diagnostics ROM in MAME sometime, to convince myself the RAM banking and MTX500 is correct.
- Nigel

BBC Model B, ATPL Sidewise, Acorn Speech, 2xWatford Floppy Drives, AMX Mouse, Viglen case, etc.

Martin A
Posts: 406
Joined: 09 Nov 2013 21:03

Re: System test rom/Board

Post by Martin A » 18 Apr 2019 22:34

Final posting for the day The menu has gained an extra function, seen here from a screen dump in the emulator while testing.
Menu.JPG
Emulation view of the menu
Menu.JPG (156.85 KiB) Viewed 450 times
The ram test is now clever enough to spot a duff multiplexer !
RamTesting.JPG
Ram test screen
RamTesting.JPG (62.69 KiB) Viewed 450 times
And last but not least, the output from the rom test
EasterEgg.JPG
Who was Caro ?
EasterEgg.JPG (298.71 KiB) Viewed 450 times
The question is now, is who is or was "Caro" and who put that message in the rom 30+ years ago ??

If you want to see that in a real MTX, run PANEL, and type in D 2BD0, break, and I to show the ASCII instead of hex.

I went back to the PDF of the source code from Andy's site, and found it hidden as a data table, called "SECTABLE" (presumably secret table?) in the MTXROM_145_190 PDF at the bottom of page 35 (listing page 1-82)

The compiled 32k image, it's laid out as system roms A B and C in order with the ramless boot rom in the last 8k
ROM build 79.zip
32k rom image
(21.56 KiB) Downloaded 18 times
If anyone wants a look, this is the source code for build 79
Test Rom Source.zip
Source file - good luck getting it assembled !
(4.94 KiB) Downloaded 19 times
It's designed to build on my homebrew assembler with the extra macro commands for stack replacement etc.

User avatar
1024MAK
Posts: 555
Joined: 24 Dec 2012 03:01
Location: Looking forward to summer, in Somerset, UK

Re: System test rom/Board

Post by 1024MAK » 18 Apr 2019 23:33

Wow! That was quick work Martin :shock:

Excellent progress and excellent work 8-) :D 👏

Mark

Pernod
Posts: 15
Joined: 21 May 2017 17:26
Location: Croydon, UK

Re: System test rom/Board

Post by Pernod » 21 Apr 2019 18:16

Thanks for posting the ROM image.

Curiously I'm getting slightly different output from the ROM test for ROM1 in MAME, any ideas why?

I'm assuming your screenshots are from an emulator, so what does a real MTX show?
0004.png
0004.png (63.65 KiB) Viewed 420 times
Last edited by Pernod on 21 Apr 2019 20:01, edited 1 time in total.
- Nigel

BBC Model B, ATPL Sidewise, Acorn Speech, 2xWatford Floppy Drives, AMX Mouse, Viglen case, etc.

Martin A
Posts: 406
Joined: 09 Nov 2013 21:03

Re: System test rom/Board

Post by Martin A » 21 Apr 2019 19:11

It looks line Mame might be initialising the video ram to zero.

The real MTX can have junk in there on boot, so my emulator doesn't bother to clear it. The test rom didn't either, so I'm getting junk on the display for codes less than 32.

On the latest build the first 32 character codes are defined blank, and the display looks much more lime Mame's

Photo this time of the real MTX rather than emulation.
new build.jpg
Garbage fixed
new build.jpg (67.79 KiB) Viewed 417 times

Pernod
Posts: 15
Joined: 21 May 2017 17:26
Location: Croydon, UK

Re: System test rom/Board

Post by Pernod » 21 Apr 2019 20:16

Martin A wrote:
21 Apr 2019 19:11
It looks line Mame might be initialising the video ram to zero.
Correct, well it doesn't randomise it first.
Martin A wrote:
21 Apr 2019 19:11
The real MTX can have junk in there on boot, so my emulator doesn't bother to clear it. The test rom didn't either, so I'm getting junk on the display for codes less than 32.
Thanks for explanation, I'm happy with MAME's results so looks good :)

When you have a final ROM I'd like to support it officially, as it's a useful tool to test against potential regression.

PS. There's a typo on the stack pointer test page 'ponter'.
- Nigel

BBC Model B, ATPL Sidewise, Acorn Speech, 2xWatford Floppy Drives, AMX Mouse, Viglen case, etc.

Martin A
Posts: 406
Joined: 09 Nov 2013 21:03

Re: System test rom/Board

Post by Martin A » 21 Apr 2019 22:09

ROM Update to build 117

There's now an option to run a monitor type facility to display and write the ram. As with the rest of the rom, the dump, edit and fill routines don't use any ram themselves.
Menu117.JPG
The extra menu option
Menu117.JPG (167.56 KiB) Viewed 405 times
The monitor scrolls up from the bottom leaving reminder of the options on the top lines. The monitor doesn't change the ram paging, so running the memory test for the extra 16k on the MTX512, then the monitor, will allow examination of page 1 of memory. The rom tests and regular memory tests will all reset the ram page to zero.
Monitor117.JPG
Monitor in action
Monitor117.JPG (305.26 KiB) Viewed 405 times
The character set has had a bit of an upgrade, the previously blank codes 0 to 31 are now the inverse of 64 to 95. So the rom dump page now looks like this:
RomTest117.JPG
Updated rom dump
RomTest117.JPG (303.98 KiB) Viewed 405 times
And running on a real MTX, prior to running the monitor, the ram has been written to by the memory test routine.
dumpRamGood.jpg
The ram dump after the ram test has run
dumpRamGood.jpg (70.35 KiB) Viewed 405 times
Finally for this posting a copy of the binary for testing. At the moment the test rom is only using around half of the available space.
rom Build 117.zip
32k image for the test board
(22.17 KiB) Downloaded 19 times
PS the typo in the stack test has been fixed.

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