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Building MTXPlus+

Posted: 30 May 2014 02:26
by Dave
To start the ball rolling, here is what I am doing . . . . .

MTXPlus+

MTXPlus+ was an idea that Lez floated towards the end of 2012, the idea was to design an enhanced MTX type computer, using a selection of ICs that Lez was giving away. The original idea was that Lez would run a "Crash Z80 design course" and, in his words . . .

"The course is not designed to make you into a computer scientist it's just a fun and informal way to learn about microcomputer design and the MTX512 computer."

For various reasons, not least of which, was the apparent lack of enthusiasm from the small list of members here, the course did not go ahead, although Lez did make the intended course material available.

Nevertheless, I decided to go ahead anyway and created an area on my website to document the project:
http://www.primrosebank.net/computers/m ... txplus.htm

Although progress to date has been slow, it has now started to take shape, in no small part because Martin came on board and is now collaborating with MTXPlus. Martin is very enthusiastic and has given me the impetus I needed to move along at a reasonable pace.

Martin and I will add further posts here to describe how things are progressing, hopefully, others will join in and share what they are doing with their kits too

regards
Dave

Re: Building MTXPlus+

Posted: 30 May 2014 09:59
by Martin A
Still mostly on "background" work for the MTX+

Dave has pictures of the backplane on his site, since I didn't have the luxury of obtaining a zillion slot board from e-bay for a fiver, I hand soldered it.

http://primrosebank.net/computers/mtx/p ... ane_MA.jpg
http://primrosebank.net/computers/mtx/p ... ack_MA.jpg

The next job is to layout and build the CPU and video boards. Which will be fun!

Converting Memotech's memory map to PAL equations for 512k RAM in both CPM and MTX modes is something of a trial, comments on the first draft would be appreciated. At the moment I'm just trying to fit it into the RAM equations into a 22v10.

Re: Building MTXPlus+

Posted: 30 May 2014 10:40
by Dave
Martin A wrote: since I didn't have the luxury of obtaining a zillion slot board from e-bay for a fiver,
For comparison, photos of the "zillion slot backplane" :-)
can be seen on this page
http://www.primrosebank.net/computers/m ... us_bus.htm

regards
Dave

Re: Building MTXPlus+

Posted: 30 May 2014 11:27
by Dave
Martin A wrote:Still mostly on "background" work for the MTX+

Converting Memotech's memory map to PAL equations for 512k RAM in both CPM and MTX modes is something of a trial, comments on the first draft would be appreciated. At the moment I'm just trying to fit it into the RAM equations into a 22v10.
Here our designs differ slightly, as he said, Martin intends to put the memory decode logic in a GAL.
I intend to use the EPM7128S CPLD provided in Lez's kit.
That will be a challenge in itself, so, to get some familiarity with programming and using the CPLD before trying to go straight into the design of the MTXPlus+ glue logic, I have built a "development board" with some I/O to allow me to program and test the CPLD.
Dev_board_populated_240.jpg
Dev_board_populated_240.jpg (50.11 KiB) Viewed 2608 times
You can read about that mini-project here
http://www.primrosebank.net/computers/m ... estbed.htm

regards
Dave

Re: Building MTXPlus+

Posted: 03 Jun 2014 18:51
by Dave
Again, in the spirit of sharing what we are doing, Martin has suggested that this mini-project warrants an entry here too.

Yet more preparation before we actually get to building the real parts of MTXPlus+.

Since the project is being developed in stages, there will be a CPU board before a video board is available.
We wanted a way to see if the heart of the system, i.e., the CPU and ROM were working as expected, so we thought that a backplane diagnostic board was a good idea.

As is my wont, I made my version far more complicated than it needed to be!
There's no literal "bells & whistles" - but lots of flashing lights :lol:
diag_testing_anot_480.jpg
diag_testing_anot_480.jpg (157.58 KiB) Viewed 2600 times
We have also built adapter boards to allow the boards to be used with a standard MTX - here is mine single-stepping CPU instructions on my MTX
testing_ss_display2_480.jpg
testing_ss_display2_480.jpg (48.73 KiB) Viewed 2600 times
You can read the full details here
http://www.primrosebank.net/computers/m ... s_diag.htm

regards
Dave

Re: Building MTXPlus+

Posted: 04 Jun 2014 23:34
by Martin A
On a "slightly" smaller scale, how's this ?

It's a plug in super slow clock, as per the middle third of the schematic, to run in conjunction with the bus diagnostic's card on a flaky MTX500 I've been playing with.

It's designed to replace the 74S04 (or 74HC04) on the MTX board at position 9D

With a CMOS CPU on the MTX main board, it runs a 2.5hz. Slow enough to literally see the address bus change from instruction, to refresh to whatever, as the cpu runs.

At that rate it would take an MTX take a couple of days to come up with "Ready".

In theory it too slow for the NMOS CPU, as that's supposed to need a minimum clock speed of around 50khz, it's likely too slow for dynamic ram too, but for testing the rom, that shouldn't matter.

Re: Building MTXPlus+

Posted: 05 Jun 2014 10:52
by 1024MAK
So Martin, are you going to credit the site where your Single step/slow clock/fast clock diagram came from :mrgreen:

Mark

Re: Building MTXPlus+

Posted: 06 Jun 2014 11:11
by Martin A
Of course I will, Dave sent it to me......

Re: Building MTXPlus+

Posted: 06 Jun 2014 11:34
by 1024MAK
Martin A wrote:Of course I will, Dave sent it to me......
In that case, Dave needs to supply the credit for the web site where it came from :mrgreen:
If I can find it, I came up with my version which uses one less IC, but which does not include all the features.
When I find it, I will post it up.

Mark

Re: Building MTXPlus+

Posted: 06 Jun 2014 12:31
by Martin A
I only built the slow clock part. The 74LS04 on there needs to provide the inverters/drivers for PHI, CPU PHI and CTC PHI that 9d on the board normally supplies.

By leaving out pins 1-5 it means that the crystal and associated passive parts on the motherboard don't need to be removed. They're just driving an empty socket where pin 5 would be.

Of course 9d needs to be socketed, but that was already done as part of the timing mod, and so the pull-ups on the clock at R35 and R36 are also missing, I don't know if that would affect the workings of the clock on an un-modified system.

I found the e-mail from Dave, the Schematic came from:http://cpuville.com/cgi-bin/i/images/Z8 ... atic_2.GIF

Lots of mind boggling stuff at http://cpuville.com/.