Another build

Use this forum to describe how you are using, or planning to use, the parts kits generously donated to a number of members by Lez Anderson
Martin A
Posts: 417
Joined: 09 Nov 2013 21:03

Another build

Post by Martin A » 20 Nov 2017 16:33

OK, it's not MTX related, or even Z80, but I've got another build running from some of the "extras" I received from Lez, via Dave.

Board 1: 6502 CPU, 32k ram, 8k rom, 6mhz clock, and 74 series logic to create a memory map
Board 2: 6847 VDG, 82C55 PPI, 8k ram, 74 series buffers to isolate the ram, 14.3mhz clock divided by 4 for the VDG (at the back)
Board 3: 6522 VIA, optional 6521 PIO and LCD diagnostic screen (in the middle)
Board 1 and the keyboard
Board 1 and the keyboard
another homebuild.jpg (347.83 KiB) Viewed 2132 times
It still needs some form of storage, but it's alive. The system I really wanted back in 1981 but couldn't afford, and had to settle for a ZX81 instead.
running its first program
running its first program
it is alive.jpg (337.23 KiB) Viewed 2132 times
Theres no GAL or CPLD on the build, it's all done with logic chips, 74AHC for the most part, so the logic faster than the 74LS available as the time the original was designed. With modern static ram also havin a much better response time, I'm able to clock it 6x the speed of the original.

Screen output is currently mono, using the Y component only exactly as the original. Interestingly it's at NTSC frequencies, which no doubt cause a few issues back in the day.

User avatar
1024MAK
Posts: 569
Joined: 24 Dec 2012 03:01
Location: Looking forward to summer, in Somerset, UK

Re: Another build

Post by 1024MAK » 20 Nov 2017 21:06

Nice 8-)
Martin A wrote:Interestingly it's at NTSC frequencies, which no doubt cause a few issues back in the day.
Actually, official NTSC frequencies are very slightly different to the 525 line, 15750 Hz, 60Hz monochrome system (system 'M')
Although the ITU specified a frame rate of 30 fields, 29.97 was adopted with the introduction of NTSC color to minimize visual artifacts. PAL-M, unaffected by color encoding, continues to use a frame rate of 30.
At the same time
the horizontal line rate was reduced to approximately 15734 lines per second from 15750 lines per second.
The NTSC colour encoding system can be used on system 'I' but although tested and found to work well, the U.K. selected PAL. System 'I' and PAL colour was used in the U.K. until it was switched off after the digital switch-over. And in Brazil, their system uses PAL colour with a 525 line, 15750 Hz, 60Hz (system 'M').

Mark

User avatar
1024MAK
Posts: 569
Joined: 24 Dec 2012 03:01
Location: Looking forward to summer, in Somerset, UK

Re: Another build

Post by 1024MAK » 23 Nov 2017 14:22

I'll raise, err, lower you to:-
6502 / 65C02 chip testing board complete with a NOP generator!
6502 / 65C02 chip testing board complete with a NOP generator!
IMG_5721.JPG (1.03 MiB) Viewed 2114 times
:mrgreen:

Yes, I know that there is not a CPU in sight. That's because the ZIF socket (itself plugged into a stamped pin DIL socket) is currently in a Acorn model B computer along with a CPU on test...

Using a separate test board enables easier current (and therefore power) measurements at different clock speeds...

Mark

lezanderson
Posts: 175
Joined: 14 Aug 2012 15:31

Re: Another build

Post by lezanderson » 24 Nov 2017 12:41

:o I didn't think you could push a 6847 to 6MHz.. as they're effectively multiplexed with CPU and only rated at 1MHz ?? :? On 6809 systems they are also tied to a 74LS783 Chip.

Martin A
Posts: 417
Joined: 09 Nov 2013 21:03

Re: Another build

Post by Martin A » 24 Nov 2017 15:04

lezanderson wrote::o I didn't think you could push a 6847 to 6MHz.. as they're effectively multiplexed with CPU and only rated at 1MHz ?? :? On 6809 systems they are also tied to a 74LS783 Chip.
The 6847 runs off it's own 3.58...mhz clock (NTSC colour burst frequency). The 6502, is one of the newer WDC W65C02S models, which is rated up to 14mhz, and can go faster with the right support chips.

I'm running at 6mhz and while the memory can go faster, that's about the limit for both the 8255 and for accessing the video ram, since the 6847 is quite slow releasing the data bus to the CPU. The atom rom waits for the vertical sync before printing to avoid "snow" on the screen, so as long as the VDG is out of the way, the CPU can access the memory at it's own speed.

It's a reverse of the original setup where the atom CPU was slower than the VDG clock.

lezanderson
Posts: 175
Joined: 14 Aug 2012 15:31

Re: Another build

Post by lezanderson » 25 Nov 2017 12:11

Hi.

If you post a Bill Of Materials (BOM) list I'll see if I have any of the ICs laid around and I can send some to Dave.. Thus saving you from buying stuff unnecessarily .

Martin A
Posts: 417
Joined: 09 Nov 2013 21:03

Re: Another build

Post by Martin A » 25 Nov 2017 17:02

Here's what's currently on the 6502 system current build, in case someone else wants to build something similar. As the photo's in the first post show, 70% of it is built already, and I've got all the parts needed to complete it.

Backplane:
7-15v DC input, on/off switch, 5 and 3.3v regulators, 4 x 64 way DIN sockets.

CPU Board:
W65C02S-14 CPU
39SF010A-70 128k Flash ROM
AS6C62256-55 32k Static RAM
TL7705ACP Reset controller
6mhz 5v CMOS oscillator
74AHC138 3 to 8 decoder - Upper memory decode
74AHC138 3 to 8 decoder - I/O block decode
74AHC08 Quad 2 input and - Memory block combine
74AHC00 Quad 2 input nand - Read/write separation

The ram uses A15 as chip select, so is mapped in in the lower 32k area
The first 74AHC138 breaks the top 32k up into 4k chunks
The 2nd 74AHC138 the splits the B000-BFFF block into 8 sub blocks for up to 8 I/O devices
The 74AHC08 combines the 8000-8FFF and 9000-9FFF blocks to provide the chip select for the Video memory, and also the C000-CFFF (Basic) and F000-FFFF (MOS) blocks for the ROM chip select
The 74AHC00 combines the single "Read not Write" signal from the 6502 with the master clock to produce separate read and write signals, that only fall when it's safe to access the RAM

In addition to the CPU signals, read and write, all the I/O selects and the "external" memory selects are passed to the backplane.

I/O board 1:
8647 VDG
AS6C6264-55 8k static ram
82C55A PPI
74LS145 BCD to Decimal decoder (not available in AHC)
74HC74 Dual Flip Flop VDG clock divider
74AHC244 (2 of) three state buffer
74AHC245 three state transceiver
14.318mhz CMOS oscillator
Sufficient passive components and transistors to produce a mono composite video output

The PPI is memory mapped into the B000-B1FF area, though only uses the first 4 locations
The flip flop divides the output from the oscillator by 4 to create the VDG clock
Half the 82C55PPI and the 74LS145 provide the keyboard interface
The other half of the PPI controls various VDG mode settings and the as yet unfitted tape input/output and speaker
The VDG's memory release pin is connected to the 3, three buffer chips, and the CPU's VRAM chip select. The buffer chips prevent the VDP accesses to VRAM from affecting the CPU, memory release them prevents the VDG accessing the ram while the CPU is accessing it. If the VDG does need RAM access when blocked, a white flash appears on the screen


I/O board 2: (diagnostic board)
W65C21S-14 PIA - LCD Diagnostic display driver
W65S22S-14 VIA - Printer driver
NHD-12864WG 128 x 64 Backlit LCD display
The VIA is memory mapped into the B800 to B9FF block
The PIA is memory mapped into the B200 to B3FF block
The Display could have been directly connected to the bus at 1mhz, at faster speeds it's too slow, so the PIA provides indirect access to meet the timing requirements. Diagnostics output is currently text at 20 x 8

The diagnostic board is due to be replaced by another I/O board with
W65C22S-14 - VIA Printer driver
39SF010A-70 128k Flash ROM
74AHC08 Quad 2 input and - Memory block combine
IDE interface

The VIA will be memory mapped into the B800 to B9FF block and uses the first 16 locations.
The IDE interface will be mapped into BC00 to BDFF, though will only use the first 8 locations
There is 4k rom allocated for the disc interface controller code at E000-EFFF
However the original design also allows 4k for the floating point rom at D000-DFFF, and 4k for a "utility" rom at A000-AFFF. How that's finally going to be shared between the ROM on the CPU board and the one here is currently undecided. So the 74HCT08 may or may not be needed.
The IDE interface is currently planned to be a CFX-II 8 bit type, although a 2nd 82C55 and 74HC04 could be fitted for a CFX style 16 bit interface instead

lezanderson
Posts: 175
Joined: 14 Aug 2012 15:31

Re: Another build

Post by lezanderson » 27 Nov 2017 16:12

I'll have a rummage around and see what I can find :

W65C02S-14 CPU.....................................W65C02Pxx 6MhZ or better OK ??
39SF010A-70 128k Flash ROM ....................W27C010-7, 27C1001-7 OK ??
AS6C62256-55 32k Static RAM ....................Don't think I have any 55ns SRAMs only 15ns,70ns,85ns & 100ns
TL7705ACP Reset controller ...................... Got none of these
6mhz 5v CMOS oscillator .......................... .might have some oscillators.. the cheapy crystal type two pin ??

Only have HC (CMOS) 74xx type
74AHC138 3 to 8 decoder - Upper memory decode
74AHC138 3 to 8 decoder - I/O block decode
74AHC08 Quad 2 input and - Memory block combine
74AHC00 Quad 2 input nand - Read/write separation

I/O board 1:
8647 VDG......................................6847 >> EF6847/HD6847/MC6847 ??
AS6C6264-55 8k static ram >>.............will any 70ns or better DIP28 SRAM do such as HM62256-7 or UM61256-15
82C55A PPI.....................................got some of these.. in 5 MHz and 8MHz

Will have to look to see if I have any of these :

74LS145 BCD to Decimal decoder (not available in AHC)
74HC74 Dual Flip Flop VDG clock divider
74AHC244 (2 of) three state buffer
74AHC245 three state transceiver
14.318mhz CMOS oscillator............probably not got this


I/O boards
W65C21xx W65C21S-14 PIA, W65S22S-14 VIA ............got these somewhere not sure what exact part number
Last edited by lezanderson on 30 Nov 2017 12:54, edited 1 time in total.

Martin A
Posts: 417
Joined: 09 Nov 2013 21:03

Re: Another build

Post by Martin A » 27 Nov 2017 21:22

The 65C02 is a relatively new one from WDC, I think their earlier versions were -6 or -8 and may be too slow for 6mhz use - see the math at the end !

The 6847 you sent via Dave happens to be a Motorola MC6847 part, though any of the other manufacturer's versions should operate the same.

The 82C55 is an 8mhz version.

I use DIP 8 size 4 pin can oscillators where possible, as they don't need any support components something like: https://www.mouser.co.uk/ProductDetail/ ... 2fH3zJ0%3d Using the twin lead crystals would require extra passive parts, as well as a couple of gates from a 74HC04 or other inverter.

I used AHC parts for speed, there's no reason why HC wouldn't work, at a slower speed - 4mhz ought to be possible, but not a lot faster though.

Here's the math, persons of a nervous disposition should look away now.

To run at 6mhz, the cycle length is 166.7 ns. The modern 65C02 takes a maximum of 30ns to setup the address, leaving 136.7 for everything else to happen.

The 32k ram chip has the easiest time of it, that's decoded off A15, so anything faster than 136ns will do

The rom has to be decoded through the 138 and the 08. using HC parts, the decode would be 64ns leaving only 72 for ROM, using AHC, the decode time is only 20ns, so 116ns or better will do

The video ram has the worst timing of the lot, decode is through the 138 and 08 as per the rom, BUT 80ns has to be allowed for the VDG to tristate its address lines That leaves only 36ns for the ram. On a worst case scenario my current setup shouldn't work, as it would need an extra 20ns or so, limiting the system to 5 and a bit mhz. In practice everything performs better than the data sheets maximums and allows it to work.

SO - using HC parts and 70ns ram, the numbers would be:
30ns = 65C02 address setup time
39ns = 74HC138 propagation time
25ns = 74HC08 propagation time
80ns = MC6847 to release the address bus
70ns = Memory access time
244ns total

Giving a maximum CPU speed to 4mhz as that has a 250ns cycle time. If the older CPU's have a slower setup time, then they might or might not work at 4.

The *244 and *245 chips could be HC parts, as they're switching at the same time the VDG is releasing the address bus, and 80ns is plenty of time for them to do that.

The 74HC74 is just doing clock division, so the time it takes to switch doesn't matter. Likewise the BCD to decimal - that's driving the keyboard sense lines, and has pull-up resistors so that the LS chip can co-exist with the CMOS ones.

lezanderson
Posts: 175
Joined: 14 Aug 2012 15:31

Re: Another build

Post by lezanderson » 30 Nov 2017 12:21

I've got some EPM7032SLC44-10 & EPM7064SLC44-10 (fixed 10ns propagation time, 32 I/O lines) CPLDs... these might replace your rather slow 74xx stuff.. :idea:

Post Reply