Z80 Special Reset

About original Memotech hardware.
Post Reply
Tony Brewer
Posts: 108
Joined: 08 Jan 2014 20:50

Z80 Special Reset

Post by Tony Brewer »

Did you know the Z80 has two types of reset, normal and special? No? Well I didn't either until last month. An in-depth study of the Z80 special reset has been completed and please click on the link below for full details.
http://www.primrosebank.net/computers/z ... _reset.htm

If you were wondering why Dave has been a bit quiet lately he's been slaving away doing special reset tests. Many thanks Dave!
User avatar
1024MAK
Posts: 757
Joined: 24 Dec 2012 03:01
Location: Looking forward to summer, in Somerset, UK

Re: Z80 Special Reset

Post by 1024MAK »

I did wonder how the IDE worked. I presume (not found time to read up yet) it uses the Special Reset.

Somewhere in a technical question and answer section, Zilog say that really, the external control inputs should be considered to be synchronous (I think Reset was one input that was being referred to). Now we know why :mrgreen:

So thanks for supplying this information :D

BTW, how did you start looking into this? What sparked the search?

Mark
:!: Standby alert :!:
“There are four lights!”
Step up to red alert. Sir, are you absolutely sure? It does mean changing the bulb :!:
Looking forward to summer in Somerset later in the year :D

Not as many MTXs as Dave! :lol:
Tony Brewer
Posts: 108
Joined: 08 Jan 2014 20:50

Re: Z80 Special Reset

Post by Tony Brewer »

It's the Z80 Family Questions & Answers (http://www.z80.info/zip/ZilogProductSpe ... 29-143.pdf) that says /INT, /NMI, /BUSREQ, /WAIT and /RESET should be synchronized to the system clock and /INT and /RESET certainly were in the special reset logic (other signals not needed).

It was finding out about the patent that sparked the interest in the special reset. One thing I didn't mention in my report is that for 1T and 2T normal reset pulses it takes 3T from last rising edge of clock when /RESET is low to start of fetch from address zero, which is exactly as specified in the databooks, which is why I didn't mention it! :mrgreen:

Something not tested was NMI and special reset. If /NMI goes low when /RESET is low during a normal reset the CPU does not ignore the /NMI signal and it will be accepted at the end of the first instruction after the reset.
Post Reply