About original Memotech hardware.
- Posts: 62
- Joined: 08 Jan 2014 20:50
TBC wrote:The VDP datasheet says:
Note: Enabling bit 7 (actually bit 0/LSB) in the TMS9928A/9929A causes A-Y and B-Y to go to the sync level only when all planes in front of the pixel under question are transparent.
I have no idea what they mean by this.
is an error and should be R-Y
. More from the datasheet:
The last and lowest priority plane is the External VDP Plane. Its image is defined by the external VDP input pin which allows the TMS9918A to mix the external video signal internal to the chip.
This mixing must occur outside of the chip for the TMS9928A and TMS9929A. This is achieved through the colour difference outputs swinging to a special level not used by the colour difference signals in normal operation. This occurs when bit 7 of Register 0 is set high. External mixing circuitry is required to detect this change in the level of the colour difference signals and then switch from the VDP signals to an external source's signals.