*** M E M O R U M ***

http://primrosebank.net/computers/mtx/p ... magrom.htm

Martin has designed a nice external ROM board and I would like to get one.

If there is enough interest, it may be worth considering getting some professionally made, using the same source as Andy, the board would likely cost <£5.

Is there any interest in going that way?

Regards
Dave

Oh yes!

I would be interested in two boards.

Mark

About the ROM board. Having had a quick look, I think even if we stay with "TTL" logic chips and one ROM, the chip count can be reduced by at least one, may be more .

Mark

Hi Mark,

Maybe you could describe what you're thinking and Martin could take a look at it?

Regards
Dave

Of course

Details soon...

Mark

Okay, this draft amendment schematic reduces the chip count by two .
U1, U6, U8 stay the same type (but U1 and U8 have some wiring changes) as per Martin's schematic.
U2 has now been changed to a 74LS00 NAND chip.
U3 has been deleted.
U4 has now been changed to a 74LS30 NAND chip.
U5 has now been changed to a 74LS30 NAND chip, but if preferred can stay as a 74LS138 (just use Martin's schematic).
U7 has now been changed to a 74HCT374 or a 74HCT574 (these both provide the same function, but have different pin-outs).
U9 has been deleted.
RN1, a 4.7k resister network has been added (7 pin 6 resistor network or larger). Normal resistors can be used instead. As the latch now used (U7) does not have a clear/reset input, the "firmware" running in "ROM7" (address block 02000h to 03FFFh)
of the EPROM/FLASH (U8) should make sure that the correct value is latched before accessing the EPROM/FLASH (U8) as "RAM".
There is no problem accessing the correct address range when the EPROM/FLASH (U8) is accessed as "ROM7" (address block
02000h to 03FFFh), as when address line A14 is low, U2A inverts this signal and it is applied to the three state /OE input of the latch
(U7) which disconnects the outputs and puts them into a high impedance condition. This allows resistor network (RN1) to pull down
the address lines A14 to A19 of the EPROM/FLASH (U8) selecting the lower memory block.

Hopefully my brain was fully operational when I doodled this and I have not made any logic (or other!) errors. Feel free to shout out
if I have dropped a boo-boo

Mark

Hi Mark,

Thanks for that, I'll pass the info on to Martin,

Regards
Dave

@ Mark,

Replacing the 74xx20 and 74xx138 with a 74xx30 and one of the unused gated on 74xx32 seems so obvious now you've mentioned it.

The trick with the 74HCT374 and the resistor pack, just shows the huge gaps in my knowledge, I just mirrored the paging system Memotech used.

One thing I was curious about, but couldn't be sure I understood, and as my test bed MTX has no PAL I chose not to try and use it, is the *GROM signal on the edge connector.

Is it a active low from the MTX for ROM 7, or is it an active low from the expansion that says a game cartridge is fitted, and forces the paged ROM access so select page 7? (page 226 of the new manual) that combination of resistors and diodes is doing something...

If it IS a active low for ROM 7 than U5 can be eliminated too. If its the other then it would break any game that relies on ROM routines in that area, and possibly the controller software too as that uses a couple of RST's in initialising.

Martin, Mark,

I wrote this page when I was trying to understand the MTX ROM select logic...

http://www.primrosebank.net/computers/m ... m_mtx4.htm

E&OE excepted of course

Hopefully, it is on the right lines - as ever, feedback welcome

Regards
Dave

Not having looked at a schematic of a game cartridge (let alone getting my hands on a real game cartridge), I cannot be sure if they use /GROM.

However, looking at schematic for the MTX main board, these are my thoughts...

First of all, keep in mind that R0, R1 and R2 originate from a 74LS273 latch (5A) and that they should not be driven by any external circuitry.

Diagram from Dave's site:


The way that resistor R13 (4.7k) and the three 1N4148 diodes works is as a wired AND gate.

If R0, R1 and R2 are all logic high (logic 1), none of the three 1N4148 diodes will conduct and resistor R13 (4.7k) will pull input pin 9 of inverter 6B (74LS04) and input pin 12 of NAND gate 5B (74LS00) high.

If either R0, or R1 or R2 go low, one (or more) of the three 1N4148 diodes will conduct, which will pull pin 9 of inverter 6B (74LS04) and input pin 12 of NAND gate 5B (74LS00) low.

So the /GROM output can only go active if R0, R1 and R2 are high and the output O2 from the PAL (6A) is low.

This looks like it was added because of a limitation in the PAL (6A) (not enough pins) or because maybe the /GROM signal was added as an after thought.
It would need testing to confirm that /GROM does what we expect, as it does depend on the logic equations in the PAL being correct.

Mark