Re the crib sheet, a couple of things about the VDP section.
The VDP registers for Graphics mode 2 should be
Register 3 - FF
Register 4 - 03
The TI documentation says for graphics mode 2 the LSB's should all be one's instead of 0. The only valid values for graphics 2 are supposed to be 7F or FF for register 3 and 3 or 7 for register 4.
I found out why on a MSX site, the lower bits of both R3 and R4 get ANDed in the hardware, R3 with the upper data bits, R4 with the upper address bits.
R3 I've not played with.
R4 is useful if you're using Graphics 2 in character mode rather than as a bitmap. effectively bit 0 controls the middle 3rd of the display, bit 1 the lower third.
If the bit is set that third of the screen has it's own character definitions, if it's clear the definitions for the top third are used instead. The top third always uses it's own characters.
You can play with this in basic, print something on the top 1/3 of the screen, then set R4 to zero ie:
Code: Select all
10 VS 4: CLS
20 PRINT " HELLO"
30 OUT (2),0: OUT (2),128+4
40 GOTO 40
And you'll see 3 Hello's instead of 1
For setting up the VDP
Setting up to read data, send the low byte first, bits 6 and 7 of the 2nd transfer need to be zero, ie (high byte) AND 3F
Setting up to write data, again low byte first, for the high byte bit 7 is clear, bit 6 is set , ie ((high byte) AND 3F) OR 40
For register setups you send the data first, the 2nd transfer needs bit 7 set, ie (register number) OR 80. See the example above.
Trying to mix and match reading and writing to the VDP without the correct setups can do "unexpected" things.