*** M E M O R U M ***

Hi,

can anyone please shed some light on how DRAM memory refresh is done on the MTX5xx please?

With a bit of googling, I see that the Z80 R register was intended for DRAM refresh, but only supported 7 bits, i.e., allowing 128 row addresses (16k), the RFSH signal does not seem to be used on the MTX board anyway - although it is on the bus. Can anyone help me understand this please?

Regards
Dave

It's all done by special mirrors and dilithium crystals inside the DRAM chips via a RAS hyperlink thread. When the Z80 wants to perform a refresh, via a pulley, it tugs the RAS line and (assuming no snags occur, which would result in a meltdown failure) this tilts the mirror which allows the dilithium crystal to irradiate the DRAM memory cells. This radiation refreshes the parts that other radiation cannot reach. Hence the term refresh. Here is a video that explains it all...

Mark

Aah, now I understand prefectly ... hic !

Here are some useful information sources:-

Wikipedia - DRAM
Memory Basics
Memory Devices
DRAM TECHNOLOGY
Introduction to DRAM
Z80 INTERFACING TECHNIQUES
1984 MOS Memory Data Book
Understanding DRAM Operation
Ram Guide


Mark

Thanks a lot Mark,

I had found a number of those links, but not others - off to check them out . . .

regards
Dave