NTSC/PAL VDP setup?

[Crazyboss]

Hi

I Follow another Facebookgroup for the SORD computer, which had the same hardware as the Memotech, exept from a lower clock at the CPU. 3.57mhz.

The guys there talk about have to patch games written for NTSC to PAL. Like A bit have to be diffirent while setting up the VDP registers.

That is new INFO to me, the game they talk about is actually POWERPAC which i converted to the Memotech some years ago. They said the original game will not run on PAL hardware, but I did not modify any thing about the VDP setop to make it run at Memotech hardware (only tested on PAL), I also tested on Colecovison which I only tested on NTSC hardware.

The SORD computer came out before the Memotech, could they use another earlier version of the VDP?

I am quite sure the guys published the ColecoVision version of the Powerpac (Renamed Super pacman) tested the game at both PAL and NTSC ColecoVIsions and ADAM computers.

I know at the TMS9938 and 9958 you could change the PAL/NTSC mode by a register bit.

Also should there be a problem running Memotech Games on NTSC hardware, I am quite sure Memotech did not have special NTSC versions of the Games for the NTSC market, we know MIKE have a NTSC Memotech, but not sure how many was sold to the US.

[thewiz]

There are number of 9918 chips, e.g. 9928 and 9918A, specifically for NTSC or PAL. However the border should take up the difference as the resolutions are the same, 256 x 192

However depending on the clock speed supplied to the 9918 compared with the clock speed of the CPU would mean extra/fewer cycles needed between outs?

Of course this is all just off the top of my head

[Martin A]

Text mode on the 9918(A)/28A/29A shouldn't cause any issues on either clock rate, as the minimum separation between VDP accesses is 2us. That's 8 cycles at both 3.58 and 4 mhz

Graphics modes however the data sheet says 8us is required, so a 3.58mhz CPU has to leave 29 cycles. The 4mhz CPU has to leave 32. That's for data accesses.

Those 3 extra cycles could be the difference between a game working normally with the CPU driven off the NTSC clock, and having a corrupted display at the speed the MTX runs at.

The V9958 we use in the MTXplus has the option to insert CPU wait states between data accesses if the 2nd access arrives before the first is complete. That's a part what allows the faster clock speed without currupting the display.

The NTSC/PAL bit is more of an influence over the VDP interrupt rate and screen shape than the CPU to VDP transfer timing. For things like Basic where the VDP interrupt isn't used, I prefer NTSC mode as there's less space "wasted" for the border.

[thewiz]

Could the patch be more to do with interrupt driven sound/music? As the VDP interrupt will be different, i.e. 50Hz or 60Hz, the interrupt routine will need changing.

I think it's, skip every 6th interrupt. It does mean sound from every 5th interrupt is twice as long. That makes 5 * 20ms = 100ms = 6 * 16.6ms = 100ms

[Crazyboss]

I really dont know, but a guy at the SORD facebookpage said if he clear bit 0 at reg.0 the screen on a sord computer will go out of sync.

But that also lead me to another question, if MIKEs NTSC Memotech was a prototype or they really sold them in USA and Canada?

[Dave]

Yes, they were sold in the US

with a different UHF modulator, VDP and video board

[Martin A]

Bit 0, of register 0, is the external video enable. I would have thought that was meaningless on a 9928A or 9929A ??? as the composite video input pin was removed to allow for the colour difference signals.

[Crazyboss]

Ok, but I assume in very limited numbers.

I only know about MIKEs NTSC Memotech, I assume all the Computers in the Memotech Hardware Survey, are PAL versions.

Yes, they were sold in the US

with a different UHF modulator, VDP and video board

[Dave]

There are only 2 US models in the list so far

[TBC]

The VDP datasheet says:

Note: Enabling bit 7 (actually bit 0/LSB) in the TMS9928A/9929A causes A-Y and B-Y to go to the sync level only when all planes in front of the pixel under question are transparent.

I have no idea what they mean by this.

The japanese games that goes out of sync on a PAL Sord M5 has bit 0 = 0, meaning external VDP input is turned off. This seems like a logical thing to do on a NTSC game, since they probably don't want any external input. Why PAL machines need this bit set is a mystery though.
Also enabling the external input when playing on NTSC is of course bad.